Instruction Set Extension Through Partial Customization Of Low-End Risc Processor

This paper covers the design technique of an enhanced Reduce Instruction Set Computer (RISC)-based processor core using application-specific instruction-set processor (ASIP) methodology. The processor core, called UTeMRISC03, is essentially a synthesizable processor written in Verilog HDL with a 16-bit data path and a 22-bit wide instruction. Using ASIP methodology, the processor architecture is modified and expanded with the aim to perform multiply-accumulate (MAC) function. To embed the MAC function to the processor core, arithmetic logic unit (ALU) modules are modified and a new customized instruction set is generated for programmers to assess the MAC functions. The modified processor architecture is verified through simulation using CPUSim and implemented on Xilinx’s Spartan-3AN FPGA board. An assembly test program is developed to assess the MAC calculation accuracy and the outputs are observed through the simulator and the integrated logic analyzer using ChipScope Pro. The enhanced RISC processor has successfully executed the MAC operation in one clock cycle with only 30% more resource utilization compare to its predecessor. This all-inclusive design methodology covers hardware/software partitioning that would reflect the advantages in implementing soft-core processor in FPGA for fundamental DSP applications.